Electronic devices, such as semiconductor devices, memory chips (e.g., dynamic random-access memory (DRAM) devices), microprocessor chips, and imager chips, can include one or more timing circuits. For example, the electronic devices, such as semiconductor dies, can include one or more delay locked loops (DLL) in an input/output (IO) circuit configured to process external and internal clock signals. The DLL generally operates to generate a stable output signal from an input signal (e.g., clock signal). The DLL can generate the output signal based on controlling/adjusting phase (e.g., time delay) of the externally provided input signal.
The DLL can include a delay line configured to provide variable adjustments to the phase of the input signal. However, in traditional DLL, the delay line can consume relatively large amounts of power, both active and standby. Further, the delay line can be a major source of clock jitter. In some traditional designs, the delay line can provide a relatively large (e.g., relative to other components within the DLL or the clock circuit) impact to the total power consumption of the IO circuit. The power consumption can increase at lower data rates, since longer delay line may be activated to support the lower data rate.